1. Field of the Invention
This invention relates to data processing systems and more particularly to a general purpose computer system having an instruction fetch and execute mechanism having a look ahead feature employing prefetch, concurrency and pipe line computer concepts of instruction fetch and execution.
2. Description of the Prior Art
There are many computer systems employing look ahead features in instruction fetch and execution. They have variously been described in the prior art as instruction prefetch, instruction overlap, instruction concurrency, assembly-line processing and pipe line processing. Some typical examples are listed below.
In U.S. Pat. No. 3,254,329, issued May 31, 1966, an arrangement is disclosed for permitting a plurality of different steps associated with a plurality of different instructions to be carried out simultaneously. In this particular system, there is provided at least two advanced instruction registers, a plurality of addressable accumulator registers and an arithmetic unit. The instruction format contains a signal address of an addressable accumulator register which contains an operand to be manipulated by the arithmetic unit and also the address of the accumulator register which is to store the result of the computation. Additional bits of the instruction indicate the address in main memory of an operand to be processed or alternatively indicates an address to which control is to be transferred. Further additional bits represent the address of another addressable register which stores a value used to modify the main memory address of the operand to be processed by the instruction. In that arrangement, during the extraction of the operand associated with the instruction to be executed, the contents of the program counter is transferred to the arithmetic unit to be incremented by one. This address output is decoded, and in the next instruction is abstracted and deposited in one of the two stage registers. In the same minor cycle but during different time periods, the adder adds the operand address of the instruction to be executed to the contents of the specified addressable accumulator register to obtain the operand from memory to be manipulated in accordance with the operation specified by the instruction to be executed and also the modification of the program counter. When the above operations have been completed, the modified instruction to be executed is stored in the second instruction register and the succeeding instruction is extracted and stored in the first storage register. Subsequently, in the same manner, a new instruction is extracted after the incrementing of the program counter and stored in the first instruction register when the previous instruction has been transferred to the second instruction storage register and the instruction to be executed is almost completely executed. Thus, the extraction of other instructions and the processing thereof may occur during the execution of a previous instruction. This patent also discloses means for comparing the address of the result stored against the addresses of the operands specified in the two instructions stored in the storage registers for determining whether or not the above overlap operation should continue without interruption. If the comparison shows equality between the addresses of the result and either of the operand addresses in the next two instructions, then the overlap operation is modified. If the result is the same as the address of the addressable accumulator register to supply an operand for the instruction to be next executed, the overlap operation is not modified and the results being computed are transferred directly back to the arithmetic unit for further processing.
This reference shows an overlap operation wherein an instruction fetch of a succeeding instruction precedes the completed execution of a previously extracted instruction. The address of the instruction which designates the contents of the addressable accumulator register storing an operand for processing by the arithmetic unit is stored in the register until such time as the arithmetic unit has computed a result based on this instruction for comparison with either of the operand addresses and the next two instructions. Although instructions are immediately available to the processor after completion of the currently executing instruction, there may still be loss of time in instruction execution due to the fact that an arithmetic unit may be performing an arithmetic operation in accordance with an instruction taken from main memory while the next instruction although taken out of main memory and available, remains idle even though it does not involve an arithmetic operation being performed by the currently executing instruction. U.S. Pat. No. 3,202,969 takes note of the above problem in loss of time and provides for the extraction of an instruction from memory and its execution initiated while the arithmetic operation of a currently executing instruction is taking place.
A further prior art reference along these lines is an article entitled, "System Design of a Small Fast Digital Computer", IEEE, December, 1963 which discloses an advanced control or look ahead computer arrangement for processing more than one instruction at a time. The arrangement includes a control unit which comprises an instruction control for fetching instructions from a memory well in advance of their execution, operand control which modifies the addresses of operands and calls for the operands and an arithmetic control which executes the function specified by the instructions on the operands.
Still another prior art reference along these lines is U.S. Pat. No. 3,162,841, issued Dec. 22, 1964 which provides storage registers for storing instruction addresses and operand levels prior to execution and an advanced adder operative to compute the address of the next instruction such that when the instruction contained in one of the look ahead registers is transferred to the arithmetic unit for execution, the instruction address in an associated look-ahead instruction counter, which represents the address of the next instruction, is transferred to an instruction counter buffer wherein the buffer contains the address of the next instruction to be executed during the execution of any given instruction.
Perhaps the best example of a computer system utilizing the pipe line computer principle is to be found in an article entitled, "The IBM System/360 Model 91: Machine Philosophy and Instruction Handling" IMB Journal, January, 1967, pages 8-24. The subject article mentions that the primary organizational objective for high performance is concurrency and to overlay the separate instruction functions to the greatest degree possible. A diagram on page 9 of the reference illustrates the concurrency among successive instructions. It can be seen that a second instruction may be accessed prior to the decoding and generating of the operand address and fetching of the operand associated with a first instruction. This pipe line processing technique sometimes referred to as assembly line processing can increase the internal computational performance of a computer machine by one or two orders of magnitude over conventional processing. However, the techniques suffer mainly in such processing applications as list processing, branching and interrupts and is due primarily to the fact that simple communication between adjacent assembly line stations is inadequate. (See second paragraph of second column of page 12, of the January, 1967, IBM Journal).
Since it has been demonstrated that approximately 33 percent of all executed instructions are branch instructions, improvement in look ahead features which provides better communication from the last step of one instruction to the first step of another instruction is desirable.